IP Overview

Fermionic Design offers wide portfolio of PPA optimized SERDES IPs, wide-range PLLs and Analog-Glue IPs in various nodes.

Fermionic Design IPs are highly programmable, developed using robust design flow and comes with after-sales integration support as well as documentation.

General purpose Frac-N synthesizers, special purpose PLLs (Zero-Delay-Buffers) and Clock-Distribution

Fermionic provides a configurable PLL-Core with ring or multi-gear LC VCO for clocking needs of SoC. Our PLL-core has been verified in a SERDES-applications.

 

Our PLLs product-line includes:

Fractional-N PLL core: Programmable, general purpose frequency synthesizers.

  • PPA optimized single/dual supply support using integrated LDOs

  • Jitter performance meeting common wireline communication standards such as PCIe Gen5/Gen4/Gen3, USB4.0

  • Supports Spread spectrum modulation

  • Integrated 24-bit delta-sigma modulator: Frequency resolution < 0.1ppm

  • Optional support for Xtal interface

 

 

Zero-Delay-Buffer PLL Cores for Multi-node Clock-distribution

  • ZDB-PLL core supporting spread-spectrum tracking

 

Compact low-area ring PLLs: General purpose core-supply programmable PLL-core

 

Multi-Phase PLL cores

  • Providing accurately spaced phase-outputs in source-synchronous data-interfaces

Deliverables

GDSII, CDL Netlist
Verilog Model with loop dynamics
Liberty timing models (.lib)

LEF layout abstract

Application Note

User-guide

Integration support