IP Overview

Fermionic Design offers wide portfolio of PPA optimized SERDES IPs, wide-range PLLs and Analog-Glue IPs in various nodes.

Fermionic Design IPs are highly programmable, developed using robust design flow and comes with after-sales integration support as well as documentation.

Analog General Purpose IPs


  • Bandgap Reference 

  • LDO, Power-management and supervisory control IPs

  • General Purpose ADC

  • CML buffers and multiplexers for low-jitter on-chip clock distribution

Deliverables

GDSII, CDL Netlist
Verilog Model 
Liberty timing models (.lib)

LEF layout abstract

Application Note

User-guide

Integration support