Delivering Custom IC Solutions from Concept to Success
Fermionic Design offers wide portfolio of PPA optimized SERDES IPs, wide-range PLLs and Analog-Glue IPs in various nodes.
Fermionic Design IPs are highly programmable, developed using robust design flow and comes with after-sales integration support as well as documentation.
Analog General Purpose IPs
LDO, Power-management and supervisory control IPs
General Purpose ADC
CML buffers and multiplexers for low-jitter on-chip clock distribution
GDSII, CDL Netlist
Liberty timing models (.lib)
LEF layout abstract