Delivering Custom IC Solutions from Concept to Success
IP Overview
Fermionic Design offers wide portfolio of PPA optimized SERDES IPs, wide-range PLLs and Analog-Glue IPs in various nodes.
Fermionic Design IPs are highly programmable, developed using robust design flow and comes with after-sales integration support as well as documentation.
General purpose Frac-N synthesizers, special purpose PLLs (Zero-Delay-Buffers) and Clock-Distribution
Fermionic provides a configurable PLL-Core with ring or multi-gear LC VCO for clocking needs of SoC. Our PLL-core has been verified in a SERDES-applications.
Our PLLs product-line includes:
Fractional-N PLL core: Programmable, general purpose frequency synthesizers.
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PPA optimized single/dual supply support using integrated LDOs
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Jitter performance meeting common wireline communication standards such as PCIe Gen5/Gen4/Gen3, USB4.0
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Supports Spread spectrum modulation
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Integrated 24-bit delta-sigma modulator: Frequency resolution < 0.1ppm
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Optional support for Xtal interface
Zero-Delay-Buffer PLL Cores for Multi-node Clock-distribution
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ZDB-PLL core supporting spread-spectrum tracking
Compact low-area ring PLLs: General purpose core-supply programmable PLL-core
Multi-Phase PLL cores
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Providing accurately spaced phase-outputs in source-synchronous data-interfaces
Deliverables
GDSII, CDL Netlist
Verilog Model with loop dynamics
Liberty timing models (.lib)
LEF layout abstract
Application Note
User-guide
Integration support